CAN Bit Timing Calculator
Find CAN and CAN FD prescaler and segment values for a target bitrate and sample point, with ready register values for bxCAN, SJA1000, MCP2515 and M_CAN.
Clock is the APB1 peripheral clock, not the CPU clock. Register fields store value − 1.
The clock feeding the CAN peripheral.
CiA recommends 87.5%, or 75% at 1 Mbit/s.
Bit time
8 time quanta × 250.0 ns = 2000.0 nsSJW is 1 quantum, so the controller can stretch or shorten a phase segment by up to 250.0 ns per bit to stay in step.
Register values
CAN_BTR0x00050008SJW=0, TS2=0, TS1=5, BRP=8 (each field stores value − 1)Alternatives
Ranked by bitrate accuracy, then by how close the sample point lands. Select a row to see its registers.
| BRP | TSEG1 | TSEG2 | SJW | Quanta | Sample | Error | Tolerance |
|---|---|---|---|---|---|---|---|
| 9 | 6 | 1 | 1 | 8 | 87.5% | exact | ±0.49% |
| 4 | 15 | 2 | 2 | 18 | 88.9% | exact | ±0.43% |
| 8 | 7 | 1 | 1 | 9 | 88.9% | exact | ±0.43% |
| 4 | 14 | 3 | 3 | 18 | 83.3% | exact | ±0.65% |
| 6 | 10 | 1 | 1 | 12 | 91.7% | exact | ±0.32% |
| 6 | 9 | 2 | 2 | 12 | 83.3% | exact | ±0.65% |
| 8 | 6 | 2 | 2 | 9 | 77.8% | exact | ±0.87% |
| 5 | 11 | 2 | 2 | 14 | 85.7% | 2.86% | ±0.56% |
| 7 | 8 | 1 | 1 | 10 | 90.0% | 2.86% | ±0.39% |
| 5 | 12 | 1 | 1 | 14 | 92.9% | 2.86% | ±0.28% |
| 7 | 7 | 2 | 2 | 10 | 80.0% | 2.86% | ±0.78% |
| 5 | 12 | 2 | 2 | 15 | 86.7% | -4.00% | ±0.52% |
How a CAN bit is divided
CAN does not sample a bit in the middle. Each bit is divided into a whole number of time quanta, and those quanta are grouped into segments that let every node stay synchronised without a shared clock line:
- SYNC_SEG — always exactly one quantum. Edges are expected to fall inside it, and that is how nodes detect drift.
- PROP_SEG — covers the round trip along the bus and through both transceivers, so a node does not sample before the far end has settled.
- PHASE_SEG1 and PHASE_SEG2 — absorb clock differences. The controller lengthens PHASE_SEG1 or shortens PHASE_SEG2 by up to the jump width to pull itself back into step.
The bus is sampled at the boundary between PHASE_SEG1 and PHASE_SEG2. Most registers do not expose PROP_SEG and PHASE_SEG1 separately; they combine them into TSEG1, with TSEG2 holding PHASE_SEG2. The bit time is then:
bit time = (1 + TSEG1 + TSEG2) × TQ, where TQ = prescaler / f_clk
Why the sample point matters more than it looks
The sample point is where in the bit every node reads the bus, expressed as a percentage. Placing it late leaves more room for the signal to propagate, which is what long buses need. Placing it early leaves more of the bit after the sample point, which is what resynchronisation needs.
Nodes on the same bus should agree on it. They do not have to match exactly, but a node sampling at 60% and a node sampling at 87.5% will disagree about marginal bits, and the symptom is the worst kind: a bus that works on the bench and produces sporadic errors under electrical noise or at full load.
Bus length and bitrate
The propagation segment has to cover a full round trip, so bitrate and cable length trade directly against each other:
| Bitrate | Typical maximum length |
|---|---|
| 1 Mbit/s | 40 m |
| 500 kbit/s | 100 m |
| 250 kbit/s | 250 m |
| 125 kbit/s | 500 m |
| 50 kbit/s | 1000 m |
Signal propagation in twisted pair is roughly 5 ns per metre each way, and transceiver loop delay adds a couple of hundred nanoseconds on top. If a bus is near its length limit, moving the sample point later buys propagation time at the cost of resynchronisation margin.
Jump width and oscillator accuracy
The synchronisation jump width is the largest correction a node may apply in one bit. It cannot exceed either phase segment, and it sets how much clock drift the link survives. ISO 11898-1 gives two conditions, and the tighter one wins: the jump width must absorb drift accumulated over a single bit, and it must also absorb drift over the longest run between resynchronisations, which is thirteen bit times.
The practical consequence is a budget of a few tenths of a percent, shared between the two nodes at either end of a transfer. A ±0.5% ceramic resonator consumes the whole budget on its own, which is why CAN nodes are normally clocked from a crystal. If a design has to use a resonator, choose a configuration from the table above with a larger reported tolerance — more quanta per bit and a wider jump width both help.
Reading the register fields
Nearly every CAN controller stores its timing fields as the value minus one, because zero would otherwise be meaningless. A TSEG1 of 15 quanta is written as 14, and a prescaler of 4 is written as 3. This is the single most common source of a bus running at exactly the wrong rate, and the register values shown above already have the subtraction applied.
Watch the clock source as well. On STM32 parts the bxCAN peripheral is clocked from APB1, not from the core clock, and using the wrong one produces a bitrate off by an integer factor.
CAN FD adds a second bit timing
A CAN FD frame arbitrates at the nominal bitrate and then switches to a faster data phase for the payload, switching back before the acknowledgement. That means two independent timing configurations, each with its own prescaler and segments, and both must be consistent across every node on the bus.
Above roughly 1 Mbit/s in the data phase, the loop delay through the transceiver approaches or exceeds one bit time. Transmitter delay compensation handles this by placing a secondary sample point for the transmitter's own echo, and it is effectively mandatory at 2 Mbit/s and above.
Frequently asked questions
Every node has the same bitrate, so why do they not talk?
Matching the nominal bitrate is not enough. If the sample points differ substantially, or one node has a bitrate error its neighbours cannot absorb, nodes disagree about bit boundaries and produce form or stuff errors under load. Nodes on a bus should use the same sample point, and each should reach its bitrate exactly rather than approximately.
What sample point should I use?
CiA recommends 87.5% for bitrates up to 800 kbit/s and 75% at 1 Mbit/s, where propagation delay takes a larger share of the bit. Those are the values most stacks and tools default to, so matching them is the safest choice unless a long bus forces the sample point earlier.
How accurate does the oscillator have to be?
It depends on the configuration, which is why this calculator reports a tolerance for each candidate. Typical classic CAN settings tolerate roughly 0.4 to 0.5 percent, and that budget is shared with the node at the other end. A ±0.5% ceramic resonator therefore sits right at the limit and is a common cause of intermittent bus-off faults; a crystal at 50 ppm leaves plenty of margin.
Why must a bit have between 8 and 25 time quanta?
Fewer quanta leave too little resolution for resynchronisation, since the jump width cannot exceed the phase segments. More than 25 exceeds the field widths the original Bosch controllers implement. Modern CAN FD controllers allow far more, and the limits here follow whichever part you select.
How long can the bus be at a given bitrate?
The signal has to travel to the far node and back within the propagation segment, so length and bitrate trade against each other. The usual figures are about 40 m at 1 Mbit/s, 100 m at 500 kbit/s, 250 m at 250 kbit/s, and 500 m at 125 kbit/s, assuming standard transceiver delays.
Do I need transmitter delay compensation for CAN FD?
Yes, once the data phase runs faster than about 1 Mbit/s. Above that the loop delay through the transceiver can exceed a bit time, so the transmitter would sample its own echo in the wrong place. Enabling TDC and setting the secondary sample point is required for reliable operation at 2 Mbit/s and beyond.