I²C Pull-Up Resistor Calculator

Why the value is a window, not a number

SDA and SCL are open-drain. A device can pull a line down, but nothing drives it up — the rise is a resistor charging whatever capacitance is hanging on the bus. That puts the pull-up between two limits that come from opposite directions, and both are written into the I²C specification.

Make the resistor too small and the device cannot pull the line low enough. Each device guarantees a low level only up to a stated sink current, and below that resistance the low sits aboveV_OL and stops reading as a zero.

Make it too large and the rise is too slow. The line has to cross from 0.3·VDD to 0.7·VDD inside the mode's budget, and an RC edge that misses it gives a bus that works on the bench and fails on a longer cable or with one more device fitted.

The two formulas

The 0.8473 is not a fudge factor. An RC edge takes RC · ln(0.7/0.3) to cross the two thresholds, and ln(0.7/0.3) = 0.8473. VDD cancels, which is why a higher supply buys no rise-time headroom.

What the specification says per mode

High-speed mode is absent deliberately: it switches in an active current-source pull-up during transfers, so "what resistor" is not the question being asked.

A worked example

A 3.3 V Fast-mode bus with 100 pF of capacitance and ordinary 3 mA devices:

Rp(min) = (3.3 − 0.4) / 0.003 = 967 Ω
Rp(max) = 300 ns / (0.8473 × 100 pF) = 3.54 kΩ

So anything from about 1 kΩ to 3.5 kΩ is legal, and the familiar 4.7 kΩ is outside it. That is the single most common way this goes wrong: a value that was fine at 100 kHz is carried into a 400 kHz design without rechecking, and the bus works until the cable gets longer.

Estimating bus capacitance

Cb is the total on one line: every device's input capacitance plus the interconnect. Rough figures to start from, to be replaced by datasheet numbers where they matter:

• Device input — 5 to 10 pF each, on the datasheet as Ci.
• PCB trace — roughly 1 pF per centimetre.
• Ribbon or flat cable — roughly 50 pF per metre per conductor, which is what makes off-board I²C runs difficult far sooner than people expect.

If the estimate is load-bearing, measure instead. Fit a known resistor, look at the rise on a scope, and invert the formula: Cb = tr / (0.8473 × Rp). That also catches capacitance nobody counted.

Why the middle of the window

The two limits are a ratio, not a range with a natural centre. A value at the geometric middle,√(Rmin · Rmax), sits the same factor away from failing to pull low as it does from rising too slowly, so whichever assumption turns out to be optimistic has the same margin behind it. The arithmetic middle leans toward the upper limit, which is the one that capacitance you forgot to count will erode.

When the window's spread is under about 2×, the real answer is usually that the bus needs changing rather than the resistor: fewer devices, a shorter run, a bus buffer, or a slower mode.

Things that quietly break a working bus

• Pull-ups on more than one board. Two modules each fitted with 4.7 kΩ give 2.35 kΩ. Add a third and the parallel value can fall under the minimum, at which point the weakest device can no longer pull the line low. Breakout boards ship with pull-ups fitted far more often than not.
• Mixed supply rails. Pull-ups must go to the lowest VDD on the bus, or a 1.8 V device sees 3.3 V on its pin. Where the rails genuinely differ, the answer is a level translator, not a resistor.
• Raising the clock later. Moving from 100 kHz to 400 kHz cuts the rise budget to a third, and a resistor chosen for the slower mode is often out of range at the faster one.
• Counting only the devices. The connector, the cable, and a long trace are usually a bigger share of Cb than the chips are.