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Timer Prescaler & Period Calculator

Work out prescaler and reload values for a target timer frequency or period, ranked by the PWM resolution each split leaves, with registers for STM32 and AVR.

The usual general-purpose timer. Both registers store their value minus one.

After the bus prescaler, not the core clock.

Clock:
Target:
Prescaler2tick 27.78 ns
Reload36,00015.1 bits of PWM
Frequency1 kHzexact
Period1 ms

Register values

PSC1divide by 2; the register holds 2 − 1
ARR35999count 36000 ticks; the register holds 36000 − 1

Both registers count from zero, so each holds one less than the number of steps it produces. Writing the count itself rather than the count minus one is the most common way to end up a fraction of a percent off.

PWM duty cycle

With a reload of 36,000 the duty cycle moves in steps of 0.0028%, which is what the reload size buys you.

Compare register: 18,000gives 50.0000%, high for 500 µs

Other splits

Same frequency, different trade-off. A larger reload gives finer duty control; a larger prescaler gives a rounder tick, which is easier to reason about when the timer also measures time.

PrescalerReloadTickPWM bitsError
236,00027.78 ns15.1exact
324,00041.67 ns14.6exact
418,00055.56 ns14.1exact
514,40069.44 ns13.8exact
612,00083.33 ns13.6exact
89,000111.1 ns13.1exact
98,000125 ns13.0exact
107,200138.9 ns12.8exact
126,000166.7 ns12.6exact
154,800208.3 ns12.2exact
164,500222.2 ns12.1exact
184,000250 ns12.0exact

The whole of timer configuration

A counting timer does two divisions. The prescaler divides the peripheral clock down to a tick, and the counter advances on each tick until it reaches the reload value and starts again:

f_update = f_clk / (prescaler × reload)

The product of the two is therefore fixed by the frequency you want. Everything else is a choice about how to split it, and that choice has consequences.

Why the split matters

The reload is the number of steps the counter takes per period, which is exactly the number of positions a PWM duty cycle can occupy. Two configurations that produce identical 50 Hz output can differ by a factor of three in how finely you can set the pulse width:

PrescalerReloadTickDuty steps
2460,000333 ns60,000 (≈15.9 bits)
7220,0001 µs20,000 (≈14.3 bits)
1,1251,28015.6 µs1,280 (≈10.3 bits)

All three give 50 Hz from a 72 MHz clock. The first is the right default because it wastes nothing. The second is popular anyway, because a one microsecond tick makes servo pulse widths readable directly in microseconds — a legitimate trade of resolution for clarity when the numbers will be read by people.

The candidates above are ranked by reload for that reason, with the alternatives listed so you can take the rounder tick deliberately rather than by accident.

The minus one

Both registers count from zero, so each holds one less than the number of steps it produces. A prescaler register of 71 divides by 72; a reload register of 35999 counts 36000 ticks. The calculator shows both the logical value and the register value to keep the two separate.

This is the single most common configuration error, and its signature is a period that is consistently a little too long. At a reload of 36000 the mistake costs 0.003% and nobody notices; at a reload of 10 it costs 10% and everything breaks.

Finding the timer clock

The frequency to enter is the clock arriving at the timer, which is rarely the core clock. On STM32 the timers hang off APB1 or APB2, and there is a detail that catches people: when the APB prescaler is 1 the timer clock equals the bus clock, but for any other prescaler the timer clock is twice the bus clock. A part running its core at 72 MHz with APB1 at 36 MHz still feeds its APB1 timers at 72 MHz.

On AVR the timer clock is simply the system clock, and the prescaler is one of a fixed set rather than an arbitrary integer — which is why the reachable periods are sparse and an exact match is less often available.

Choosing a PWM frequency

Two constraints pull in opposite directions. Low frequencies give more resolution, because the reload is larger for the same clock. High frequencies avoid audible noise and visible flicker, and reduce the ripple a filter has to remove.

  • Motors and switching loads: above about 20 kHz, so the switching sits beyond hearing. Below that a driver often whines audibly at exactly the PWM frequency.
  • LEDs: a few hundred hertz is enough for a stationary light, but movement of either the light or the observer turns low-frequency PWM into visible stripes. A kilohertz or more is safer.
  • Servos: 50 Hz is the convention, with the information carried in a pulse width between roughly 1 and 2 milliseconds rather than in the duty cycle as such.

At a fixed clock, raising the frequency lowers the reload and therefore the resolution. A 72 MHz timer gives about sixteen bits at 1 kHz and about eleven at 20 kHz — still far more than most loads can distinguish.

When exactness matters

A PWM output does not care about a hundredth of a percent. A timebase does. If the timer increments a clock or enforces a protocol timeout, a 0.1% error accumulates to a minute and a half per day, and the fix is either an exact split or a different clock frequency.

For the related arithmetic on buses that carry their own timing configuration, theCAN bit timing calculator and theUART baud rate calculator cover the same kind of divisor rounding, where the tolerance for error is far tighter than it is here.

Frequently asked questions

Several prescaler and reload pairs give the same frequency. Which should I use?

The one with the largest reload, unless you have a reason to prefer otherwise. The reload sets how many steps a PWM duty cycle has, so a reload of 60000 gives roughly sixteen bits of control while 20000 gives about fourteen. The exception is a timer you also read for elapsed time, where a round tick such as one microsecond is easier to reason about than a finer but awkward one.

Why do the registers hold one less than the value I calculated?

Because both counters include zero. A prescaler register of 71 divides by 72, and a reload register of 35999 counts 36000 ticks. Writing the count itself instead of the count minus one makes the period one step too long, which is a fraction of a percent at large reloads and badly wrong at small ones.

Which clock feeds the timer?

On STM32 it is the APB timer clock, not the core clock, and it is not always the same as the APB bus clock. When the APB prescaler is anything other than one, the timer clock is twice the bus clock. Reading the core frequency and assuming the timer runs at it is a common way to end up off by a factor of two.

What PWM frequency should I use for a motor or LED?

Above roughly 20 kHz for anything that can make an audible whine, which covers most motor drivers and switching loads. For LEDs, anything above about 200 Hz avoids visible flicker for a stationary observer, but 1 kHz or more is better if the light or the eye may move. Higher frequencies cost switching losses and, at a fixed clock, resolution.

My frequency is slightly off. Does it matter?

For PWM driving a load, almost never — a tenth of a percent changes nothing you can measure. For a timebase you accumulate, it does: a 0.1% error is 86 seconds a day. If the timer drives a clock or a protocol timeout, pick a split that divides exactly, and if none exists, consider a different clock.

Can I change the reload while the timer is running?

On STM32, only safely when the auto-reload preload is enabled, which makes the new value take effect at the next update event instead of immediately. Writing ARR directly with preload off while the counter is above the new value causes the counter to run to its full range before wrapping, producing one very long period.

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