UART Baud Rate Error Calculator

Find the UART divisor for a clock and baud rate, see the error it leaves, and get the register value for AVR, STM32 and 16550-style parts.

UART family

The common case, including 16550-compatible parts. The divisor is a plain integer.

Mode

Peripheral clock (MHz)

The clock feeding the UART, not the core.

Target baud rate

Clock presets:

Divisor9f_clk / (16 × 9)

Actual baud111,111.1asked for 115,200

Error-3.55%

Bit time9.00 µsframe 8N1: 90.0 µs

Too much error. Expect framing errors, especially against another imperfect end.

Register values

Divisor9baud = f_clk / (16 × 9)

DLL / DLM0x09 / 0x00Low and high divisor latch, for 16550-style parts

Clocks that divide exactly

These reach 115,200 baud with no error at all. The odd-looking frequencies are sold precisely because they do — 11.0592 MHz is 115200 × 96.

Every standard rate at 16 MHz

Select a row to make it the target. Rates the register cannot reach are marked.

Baud	Divisor	Actual	Error
1,200	833	1,200.5	+0.04%
2,400	417	2,398.1	-0.08%
4,800	208	4,807.7	+0.16%
9,600	104	9,615.4	+0.16%
19,200	52	19,230.8	+0.16%
38,400	26	38,461.5	+0.16%
57,600	17	58,823.5	+2.12%
115,200	9	111,111.1	-3.55%
230,400	4	250,000	+8.51%
460,800	2	500,000	+8.51%
921,600	1	1,000,000	+8.51%
1,000,000	1	1,000,000	exact
2,000,000	1	1,000,000	-50.00%
3,000,000	1	1,000,000	-66.67%

Where the error comes from

A UART has no clock line. Both ends run from their own oscillator and only agree on a nominal bit time, which each derives by dividing its peripheral clock:

baud = f_clk / (oversampling × divisor)

The divisor is an integer in a register. When the clock does not divide evenly into the rate you asked for, the hardware takes the nearest whole number and you get whatever rate that produces. Everything this calculator does follows from that single rounding step.

The error is worst where the divisor is small. At 9600 baud from 16 MHz the ideal divisor is 104.17 and rounding costs 0.16%; at 115200 it is 8.68 and rounding costs 3.5%. The same clock, the same peripheral, a twenty-fold difference in error — because a fractional part matters far more when the whole number is small.

How much error a link tolerates

The receiver has no continuous synchronisation. It detects the falling edge of the start bit, then samples each subsequent bit at what it believes is the middle. In an 8N1 frame the last bit it samples is the stop bit, 9.5 bit times after that edge. If its bit time differs from the transmitter's by a fractione, the sampling point has drifted by 9.5 × e bit times by then.

For the sample to still land inside the correct bit, that drift must stay under half a bit, which puts the combined error of both ends at roughly 5%. Two things eat into that budget before you get to use it: the other end has its own error, and with 16× oversampling the sampling point itself is quantised to a sixteenth of a bit. Aiming to keep each end under 2% leaves workable margin.

Error at one end	Verdict
0%	The clock divides evenly. Nothing to think about.
Up to 1%	Reliable against a normal counterpart.
1–2%	Works, but consumes most of the shared budget on its own.
Over 2%	Expect framing errors, particularly against another imperfect end.

Why UART crystals look wrong

A 11.0592 MHz crystal seems like a strange thing to manufacture until you divide it: it is exactly 115200 × 96, so at 16× oversampling the divisor is 6 and the error is zero. The whole family works the same way — 1.8432, 3.6864, 7.3728, 14.7456, 18.432 and 22.1184 MHz are all multiples of 1.8432 MHz, which is 115200 × 16.

Round frequencies do the opposite. 16 MHz, 12 MHz and 24 MHz are convenient for everything except serial communication, because none of them divides evenly into the standard rates. This is the single most useful thing to know when picking a crystal for a board that has to talk to a PC.

When the calculator above finds a non-zero error, it lists the preset clocks that would remove it entirely.

Oversampling, and what halving it costs

Most UARTs sample each bit 16 times and take the value from the middle samples. Switching to 8× — the AVR calls it U2X, STM32 calls it OVER8 — halves the divisor, which doubles its resolution and lifts the maximum reachable rate.

What you give up is sampling margin. With 8 samples per bit, the receiver's idea of the middle is coarser and it has fewer samples to reject a glitch. On a short, clean board trace this rarely matters; on a long cable or near a switching supply it can. Use it to fix a divisor problem, not as a default.

Family notes

AVR registers hold the divisor minus one, so a UBRR of 103 means a divisor of 104. Forgetting the minus one produces a rate about 1% off at high divisors and wildly off at low ones.

STM32 folds the oversampling into the register: BRR is the full ratio f_ck / baud, which gives sixteen times the resolution of a plain integer divisor. Older reference manuals present it as a 12-bit mantissa with a 4-bit fraction, but that is the same 16-bit number written two ways. With OVER8 set, the fraction narrows to three bits and bit 3 of BRR must be left clear.

Watch the clock source in either case. On STM32 the USART runs from an APB clock, not the core clock, and taking the wrong one gives a rate off by an integer factor — which looks like garbage rather than like a marginal error.

Reading the symptoms

Complete garbage on every character usually means the rate is wrong by a large factor: a wrong clock source, a missing prescaler, or the minus-one mistake. Mostly-correct text with occasional wrong characters, or framing errors that increase with longer frames, points at a marginal divisor error instead.

If the bytes arrive but the values look wrong rather than the characters, the problem is not timing — compare the raw bytes in the hex converter and check the byte order. For a bus that does carry explicit timing configuration, theCAN bit timing calculator covers the equivalent arithmetic.

Frequently asked questions

How much baud rate error is acceptable?

Under about 2% per end. A receiver resynchronises on each start bit and then samples the stop bit 9.5 bit times later, so the accumulated drift has to stay well inside half a bit. That caps the combined error of both ends near 5%, and since the other end has its own error and the sampling point is quantised, 2% is the practical working limit for one end.

Why does 11.0592 MHz exist?

Because it divides exactly. 11.0592 MHz is 115200 × 96, so at 16× oversampling the divisor is a clean 6 and the error is zero. Every crystal in that family — 1.8432, 3.6864, 7.3728, 14.7456, 22.1184 MHz — is a multiple of 1.8432 MHz, which is itself 115200 × 16.

Why does 16 MHz struggle with 115200 baud?

The ideal divisor is 16,000,000 / (16 × 115200) = 8.68, and the register only holds whole numbers. Rounding to 9 gives 111,111 baud, which is 3.5% low — enough to cause framing errors against another imperfect end. Double-speed or 8× oversampling halves the quantisation step and brings it to 2.1%.

What do U2X and OVER8 actually change?

Both halve the oversampling ratio, from 16 samples per bit to 8. That doubles the divisor resolution, so the rounding error shrinks and higher baud rates become reachable from the same clock. The cost is that the receiver has half as many samples to find the middle of a bit, which leaves less tolerance for noise and edge jitter.

My link works at 9600 but fails at 115200. Why?

Almost always the divisor. At 9600 the divisor is large, so rounding it changes the rate by a fraction of a percent. At 115200 the divisor is small — often single digits — and rounding it moves the rate by several percent. Check the error at both rates with the same clock and the difference is usually obvious.

Does the error of both ends add up?

Yes, and in the worst case they add rather than cancel. A transmitter 2% fast talking to a receiver 2% slow presents an effective 4% mismatch. This is why a device with an internal RC oscillator, typically ±1% to ±2% over temperature, is marginal for UART even when the calculated divisor error is zero.